: Header for stm32f4_system.c file. More...

#include <stdbool.h>
#include "stm32f4xx.h"

Macros
#define	BIT_POS_TO_MASK(x) (0x01 << (x))

#define	BASE_MASK_TO_POS(m, p) ((m) << (p))

#define	GET_PIN_IRQN(pin) ((pin) >= 10 ? EXTI15_10_IRQn : ((pin) >= 5 ? EXTI9_5_IRQn : (EXTI0_IRQn + (pin))))

#define	STM32F4_GPIO_MODE_IN 0x00U

#define	STM32F4_GPIO_MODE_OUT 0x01U

#define	STM32F4_GPIO_MODE_AF 0x02U

#define	STM32F4_GPIO_MODE_AN 0x03U

#define	STM32F4_GPIO_PUPDR_NOPULL 0x00U

#define	STM32F4_GPIO_PUPDR_PULLUP 0x01U

#define	STM32F4_GPIO_PUPDR_PULLDOWN 0x02U

#define	STM32F4_TRIGGER_RISING_EDGE 0x01U

#define	STM32F4_TRIGGER_FALLING_EDGE 0x02U

#define	STM32F4_TRIGGER_BOTH_EDGE (STM32F4_TRIGGER_RISING_EDGE \| STM32F4_TRIGGER_FALLING_EDGE)

#define	STM32F4_TRIGGER_ENABLE_EVENT_REQ 0x04

#define	STM32F4_TRIGGER_ENABLE_INTERR_REQ 0x08U

#define	STM32F4_AF1 0x01U

#define	STM32F4_AF2 0x02U

Functions
void	stm32f4_system_gpio_config (GPIO_TypeDef *p_port, uint8_t pin, uint8_t mode, uint8_t pupd)
	Configure the mode and pull of a GPIO. More...

void	stm32f4_system_gpio_config_alternate (GPIO_TypeDef *p_port, uint8_t pin, uint8_t alternate)
	Configure the alternate function of a GPIO. More...

void	stm32f4_system_gpio_config_exti (GPIO_TypeDef *p_port, uint8_t pin, uint32_t mode)
	Configure the external interruption or event of a GPIO. More...

void	stm32f4_system_gpio_exti_enable (uint8_t pin, uint8_t priority, uint8_t subpriority)
	Enable interrupts of a GPIO line (pin) More...

void	stm32f4_system_gpio_exti_disable (uint8_t pin)
	Disable interrupts of a GPIO line (pin) More...

bool	stm32f4_system_gpio_read (GPIO_TypeDef *p_port, uint8_t pin)
	Read the digital value of a GPIO. More...

void	stm32f4_system_gpio_toggle (GPIO_TypeDef *p_port, uint8_t pin)
	Toggle the value of a GPIO. More...

void	stm32f4_system_gpio_write (GPIO_TypeDef *p_port, uint8_t pin, bool value)
	Write a digital value in a GPIO atomically. More...

Detailed Description

: Header for stm32f4_system.c file.

Attention

Josué Pagán Ortiz (j.pag.nosp@m.an@u.nosp@m.pm.es) Sistemas Digitales II

Macro Definition Documentation

◆ BASE_MASK_TO_POS

#define BASE_MASK_TO_POS	(	m,
		p
	)	((m) << (p))

Move a mask defined in the LSBs to upper positions by shifting left p bits

◆ BIT_POS_TO_MASK

#define BIT_POS_TO_MASK ( x ) (0x01 << (x))

Convert the index of a bit into a mask by left shifting

◆ GET_PIN_IRQN

#define GET_PIN_IRQN ( pin ) ((pin) >= 10 ? EXTI15_10_IRQn : ((pin) >= 5 ? EXTI9_5_IRQn : (EXTI0_IRQn + (pin))))

Compute the IRQ number associated to a GPIO pin

◆ STM32F4_AF1

#define STM32F4_AF1 0x01U

Alternate function 1

◆ STM32F4_AF2

#define STM32F4_AF2 0x02U

Alternate function 2

◆ STM32F4_GPIO_MODE_AF

#define STM32F4_GPIO_MODE_AF 0x02U

Alternate function mode

◆ STM32F4_GPIO_MODE_AN

#define STM32F4_GPIO_MODE_AN 0x03U

Analog mode

◆ STM32F4_GPIO_MODE_IN

#define STM32F4_GPIO_MODE_IN 0x00U

Input mode

◆ STM32F4_GPIO_MODE_OUT

#define STM32F4_GPIO_MODE_OUT 0x01U

Output mode

◆ STM32F4_GPIO_PUPDR_NOPULL

#define STM32F4_GPIO_PUPDR_NOPULL 0x00U

No pull-up, no pull-down

◆ STM32F4_GPIO_PUPDR_PULLDOWN

#define STM32F4_GPIO_PUPDR_PULLDOWN 0x02U

Pull-down

◆ STM32F4_GPIO_PUPDR_PULLUP

#define STM32F4_GPIO_PUPDR_PULLUP 0x01U

Pull-up

◆ STM32F4_TRIGGER_BOTH_EDGE

#define STM32F4_TRIGGER_BOTH_EDGE (STM32F4_TRIGGER_RISING_EDGE | STM32F4_TRIGGER_FALLING_EDGE)

Interrupt mask for detecting both rising and falling edges

◆ STM32F4_TRIGGER_ENABLE_EVENT_REQ

#define STM32F4_TRIGGER_ENABLE_EVENT_REQ 0x04

Interrupt mask for enabling event request

◆ STM32F4_TRIGGER_ENABLE_INTERR_REQ

#define STM32F4_TRIGGER_ENABLE_INTERR_REQ 0x08U

Interrupt mask for enabling interrupt request

◆ STM32F4_TRIGGER_FALLING_EDGE

#define STM32F4_TRIGGER_FALLING_EDGE 0x02U

Interrupt mask for detecting falling edge

◆ STM32F4_TRIGGER_RISING_EDGE

#define STM32F4_TRIGGER_RISING_EDGE 0x01U

Interrupt mask for detecting rising edge

Function Documentation

◆ stm32f4_system_gpio_config()

void stm32f4_system_gpio_config	(	GPIO_TypeDef *	p_port,
		uint8_t	pin,
		uint8_t	mode,
		uint8_t	pupd
	)

Configure the mode and pull of a GPIO.

  ==============================================================================
                          ##### How to use GPIOs #####
  ==============================================================================
  [..]
    (#) Enable the GPIO AHB clock using the RCC->AHB1ENR register.

    (#) Configure the GPIO pin.
        (++) Configure the IO mode.
        (++) Activate Pull-up, Pull-down resistor.
        (++) In case of Output or alternate function mode, configure the speed if needed.
        (++) Configure digital or analog mode.
        (++) In case of external interrupt/event select the type (interrupt or event) and
             the corresponding trigger event (rising or falling or both).

    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
        mapped to the EXTI line and enable it using.

    (#) To get the level of a pin configured in input mode use the GPIOx_IDR register.

    (#) To set/reset the level of a pin configured in output mode use the GPIOx_BSRR register
        to SET (bits 0..15) or RESET (bits 16..31) the GPIO.

Enable GPIOx clock in AHB1ENR

Set mode in MODER

Set pull up/down configuration

Note: This function performs the GPIO Port Clock Enable. It may occur that a port clock is re-enabled, it does not matter if it was already enabled. *; This function enables the AHB1 peripheral clock. After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters

p_port	Port of the GPIO (CMSIS struct like)
pin	Pin/line of the GPIO (index from 0 to 15)
mode	Input, output, alternate, or analog
pupd	Pull-up, pull-down, or no-pull

Return values

None

◆ stm32f4_system_gpio_config_alternate()

void stm32f4_system_gpio_config_alternate	(	GPIO_TypeDef *	p_port,
		uint8_t	pin,
		uint8_t	alternate
	)

Configure the alternate function of a GPIO.

Create a 4-bit base mask.

Shift left the mask depending on the value of the given **pin modulo 8.**
    💡 The value of pin ranges from 0 to 15. The registers GPIOx_AFRH and GPIOx_AFRL implement 8 groups of 4 bits each. In order to use the value of pin as index to select the corresponding group of bits, we can use the remainder of the division by 8.

Clean and set the bits as shown in the tutorial document.
    💡 Clean the corresponding bit on element 0 or 1 of the AFR array (e.g, GPIOA->AFR[0] for GPIOx_AFRL)
    💡 Set the given value (alternate) of the alternate function, using bit shifting, for example.

💡 You can define your own masks for each alternate function (not recommended), or you can use the macro BASE_MASK_TO_POS(m, p) to get the mask of a base mask. Example:
A base mask m equals 0x03 (0b 0000 0011 in binary) can be shifted p equals 8 positions BASE_MASK_TO_POS(0x03, 8) resulting in 0x300 (0b 0011 0000 0000 in binary).

Note: The AFR register is a 2-element array representing GPIO alternate function high an low registers (GPIOx_AFRH and GPIOx_AFRL)
AFRLy: Alternate function selection for port x pin y (y = 0..7)
AFRHy: Alternate function selection for port x pin y (y = 8..15)

Parameters

p_port	Port of the GPIO (CMSIS struct like)
pin	Pin/line of the GPIO (index from 0 to 15)
alternate	Alternate function number (values from 0 to 15) according to table of the datasheet: "Table 11. Alternate function".

Return values

None

◆ stm32f4_system_gpio_config_exti()

void stm32f4_system_gpio_config_exti	(	GPIO_TypeDef *	p_port,
		uint8_t	pin,
		uint32_t	mode
	)

Configure the external interruption or event of a GPIO.

Enable the System configuration controller clock (SYSCFG). Enable the SYSCFG by setting the bit SYSCFGEN of the peripheral clock enable register (RCC_APB2ENR). The system configuration controller is used here to manage the external interrupt line connection to the GPIOs.
    💡 As usual, you can access to the register (APB2ENR) as element of the structure RCC. You can use the macro RCC_APB2ENR_SYSCFGEN defined in stm32f446xx.h to set the bit. Look for the "RCC_APB2ENR" register in the Reference Manual if you need more information.

Associate the external interruption line to the given port. Clean and set the bits as shown in the tutorial document.
    💡 Depending on the pin number, use the register SYSCFG_EXTICR1, SYSCFG_EXTICR2, SYSCFG_EXTICR3, or SYSCFG_EXTICR4. The structure SYSCFG contains a 4-element array called EXTICR; the first element (EXTICR[0]) configures the register SYSCFG_EXTICR1, and so on.
    💡 To clean the EXTIx bits, you can create a mask depending on the pin value.
    💡 To associate the external interruption to the given port, i.e. to set the EXTIx bits, you can create another mask depending on the port value.

Select the direction of the trigger: rising edge, falling edge, or both, depending on the value of the given mode.
    💡 If rising edge: activate the corresponding bit on the EXTI_RTSR register (element RTSR) of the EXTI structure.
    💡 If falling edge: activate the corresponding bit on the EXTI_FTSR register (element FTSR) of the EXTI structure.
    💡 If both: activate the corresponding bit on both registers.

Select the interrupt and/or event request: depending on the value of the given mode.
    💡 If event request enable: activate the corresponding bit on the EXTI_EMR register (element EMR) of the EXTI structure.
    💡 If interrupt request enable: activate the corresponding bit on the EXTI_IMR register (element IMR) of the EXTI structure.

💡 You can define your own masks for each pin value (not recommended), or you can use the BIT_POS_TO_MASK(pin) macro to get the mask of a pin.

Warning: It is highly recommended to clean the corresponding bit of each register (RSTR, FTSR, EMR, IMR) before activating it.

Parameters

p_port	Port of the GPIO (CMSIS struct like)
pin	Pin/line of the GPIO (index from 0 to 15)
mode	Trigger mode can be a combination (OR) of: (i) direction: rising edge (0x01), falling edge (0x02), (ii) event request (0x04), or (iii) interrupt request (0x08).

Return values

None

◆ stm32f4_system_gpio_exti_disable()

void stm32f4_system_gpio_exti_disable ( uint8_t pin )

Disable interrupts of a GPIO line (pin)

Parameters

pin	Pin/line of the GPIO (index from 0 to 15)

Return values

None

◆ stm32f4_system_gpio_exti_enable()

void stm32f4_system_gpio_exti_enable	(	uint8_t	pin,
		uint8_t	priority,
		uint8_t	subpriority
	)

Enable interrupts of a GPIO line (pin)

Parameters

pin	Pin/line of the GPIO (index from 0 to 15)
priority	Priority level (from highest priority: 0, to lowest priority: 15)
subpriority	Subpriority level (from highest priority: 0, to lowest priority: 15)

Return values

None

◆ stm32f4_system_gpio_read()

bool stm32f4_system_gpio_read	(	GPIO_TypeDef *	p_port,
		uint8_t	pin
	)

Read the digital value of a GPIO.

TODO alumnos:

✅ 1. Retrieve the value of the IDR register.
💡 You must cast the read value to return a bool.
💡 You might use the BIT_POS_TO_MASK(pin) macro.

✅ 2. Return the value.

Parameters

p_port	Port of the GPIO (CMSIS struct like)
pin	Pin/line of the GPIO (index from 0 to 15)

Returns: true if the GPIO was HIGH; false if the GPIO was LOW

◆ stm32f4_system_gpio_toggle()

void stm32f4_system_gpio_toggle	(	GPIO_TypeDef *	p_port,
		uint8_t	pin
	)

Toggle the value of a GPIO.

TODO alumnos:

✅ 1. Read the value of the GPIO.

✅ 2. Write the opposite value in the GPIO.
💡 You might use functions stm32f4_system_gpio_read() and stm32f4_system_gpio_write() to help you.
💡 You might use the macros HIGH and LOW.

Parameters

p_port	Port of the GPIO (CMSIS struct like)
pin	Pin/line of the GPIO (index from 0 to 15)

Return values

None

◆ stm32f4_system_gpio_write()

void stm32f4_system_gpio_write	(	GPIO_TypeDef *	p_port,
		uint8_t	pin,
		bool	value
	)

Write a digital value in a GPIO atomically.

TODO alumnos:

✅ 1. Set the corresponding bit value of the BSRR register to set or reset the output depending on the given value.
💡 You might use the macros HIGH and LOW.
💡 You might use the BIT_POS_TO_MASK(pin) macro.

Note: You can use a +16 offset on the pin index and use the BIT_POS_TO_MASK(pin) macro to get the mask when you go to clear a GPIO. Otherwise, you can calculate the pin mask first and then use a 16-position left shift of the mask.

Parameters

p_port	Port of the GPIO (CMSIS struct like)
pin	Pin/line of the GPIO (index from 0 to 15)
value	Boolean value to set the GPIO to HIGH (1, `true`) or LOW (0, `false`)

Return values

None

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ BASE_MASK_TO_POS

◆ BIT_POS_TO_MASK

◆ GET_PIN_IRQN

◆ STM32F4_AF1

◆ STM32F4_AF2

◆ STM32F4_GPIO_MODE_AF

◆ STM32F4_GPIO_MODE_AN

◆ STM32F4_GPIO_MODE_IN

◆ STM32F4_GPIO_MODE_OUT

◆ STM32F4_GPIO_PUPDR_NOPULL

◆ STM32F4_GPIO_PUPDR_PULLDOWN

◆ STM32F4_GPIO_PUPDR_PULLUP

◆ STM32F4_TRIGGER_BOTH_EDGE

◆ STM32F4_TRIGGER_ENABLE_EVENT_REQ

◆ STM32F4_TRIGGER_ENABLE_INTERR_REQ

◆ STM32F4_TRIGGER_FALLING_EDGE

◆ STM32F4_TRIGGER_RISING_EDGE

Function Documentation

◆ stm32f4_system_gpio_config()

◆ stm32f4_system_gpio_config_alternate()

◆ stm32f4_system_gpio_config_exti()

◆ stm32f4_system_gpio_exti_disable()

◆ stm32f4_system_gpio_exti_enable()

◆ stm32f4_system_gpio_read()

◆ stm32f4_system_gpio_toggle()

◆ stm32f4_system_gpio_write()